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An affordable and open-source FPGA platform for the electronic control of microscope.

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Change PWM bit depth

The PWM level is currently encoded by a 8 bits value. To increase the number of steps between the minimum and maximum value, the encoding can be changed to 16 bits for instance.

  1. In au_plus_top.luc (line 139), change the bit depth to 16:

    pwm pulsewm[NUM_PWM](#TOP(254),#DIV(9),#WIDTH(16));
    dff dutycycle[NUM_PWM][16];
    
  2. In au_top.luc (line 189), change the bit depth to 16:

    dutycycle.d[reg.regOut.address-ADDR_PWM] = reg.regOut.data[15:0];
    

Now, the code on the user side should be changed to accept higher values, for instance: